1. Field of the Invention
The present invention relates to integrated circuit design, and more specifically to a method and apparatus for generating a glitch free output when selecting from multiple clock signals.
2. Related Art
A need often exists to select from multiple clock signals. For example, a device may operate using one of two clock signals having different speeds (i.e., clock period), with a slower clock signal typically being used to consume lower electrical power in durations of inactivity of the device. Thus, a higher speed clock signal may be used during normal operation and the lower speed clock signal may be used during periods of inactivity. Accordingly, the device may need to select from among multiple clock signals, and the selected output may be used to drive several other components of the device.
A multiplexor is often used to perform the selection operation. The multiplexor may receive several clock signals (xe2x80x9cinput clock signalsxe2x80x9d) as input and select one of the clock signals depending upon the value of a selection input. For simplicity of understanding it is hereafter assumed that the multiplexor receives only two clock signals, and the selection input accordingly is a binary number. However, the present invention may be used in conjunction with more than two clock signals provided as inputs. Depending on the state of the select signal (high or low) one of the two clock signals is selected to generate the output clock signal.
A glitch can result in the output clock signal particularly when a phase relationship does not exist between the input clock signals. A glitch generally refers to a pulse of a short duration. A glitch typically occurs when the multiplexor changes the selection in a short duration after a prior transition of the output signal.
Glitches are generally undesirable in that the components driven by an output signal may be implemented under the assumption that the output signal would only have pulses of at least a pre-specified duration. Glitches having a duration of less than the pre-specified duration can lead to unpredictable or erroneous results, and are thus undesirable.
Therefore, what is needed is a method and an apparatus which generates a glitch-free output when selecting from multiple input clock signals. In addition, it may be desirable to consume minimal electrical power when generating the output at least in environments (e.g., mobile devices operating from batteries) where minimizing power consumption is of particular interest.
A clock generation circuit provided in accordance with the present invention generates a glitch free output when selecting from among multiple clock signals. In an embodiment, the clock generation circuit selects either a faster clock signal or a slower clock signal depending on the logical value of a sleep signal. The sleep signal specifies whether the faster clock or the slower clock signal is to be selected.
The clock generation circuit may contain two AND gates, with a first AND gate passing through (gating) the slower clock signal if a first select signal is at high logical value. The second AND gate may pass the faster clock signal if a second select is at a high logical value. An OR gate performs a logical OR operation of the outputs of the two AND gates. A signal control block delays some of the select signal, the faster and slower clock signals to ensure that glitches are not generated on the output of any of the three gates (i.e, two AND gates and an OR gate) as described below.
According to an aspect of the present invention, the signal control block generates the two select signals such that at least a desired delay exists between transitions on the first select signal and the slower clock signal. Similarly, the second select signal is generated such that at least the desired delay exists between transitions on the second select signal and the faster clock signal. The desired delay determines the minimum pulse width. As a result, glitches (with a pulse width less than the determined minimum pulse width) are absent at the output of the AND gates.
According to another aspect of the present invention, the signal control block introduces delays into at some of the first select signal, the second select signal, the slower clock signal and the faster clock signal to avoid the occurrence of a high to low transition on one input followed by low to high transition on another input of the two inputs of the OR gate within a desired duration. As a result, glitches are eliminated at the output of the OR gate also.
In one embodiment, the signal control block comprises a first synchronizer synchronizing the sleep signal with a negative edge of the faster clock signal to generate the second select signal. An inverter inverts the second select signal to generate an inverted output. A second synchronizer synchronizes the inverted output with a negative edge of the faster clock signal to generate the first select signal.
The signal control block may further include a third synchronizer to synchronize the sleep signal with a negative edge of the slower clock signal to generate an output. The output of the third synchronizer is provided as an input to the first synchronizer. A fourth synchronizer synchronizes the slower clock signal with a positive edge of the faster clock signal to generate an output. The output of the fourth synchronizer being provided as an input to the first AND gate. As a result of the connections, the sequencing of the transitions on the slower and faster clock signals are controlled to avoid glitches at the output of the OR gate as well.
In an alternative embodiment, the signal control block ensures that a 1 to 0 transition on one of the first select signal and the second select signal precedes a 0 to 1 transition on another one of the first select signal and the second select signal, with the two transitions occurring in response to a change in value on the sleep signal. Such a feature ensures that glitches are not generated by the OR gate (when each AND gate does not generate a glitch).
The clock generation circuit of the alternative embodiment may contain two synchronizers, a third AND logic gate and an NOR gate. The third AND gate generates an output by performing an AND logical operation of an inverted value of the output of the second synchronizer and the sleep signal. The output of the third AND logic gate is provided as an input to the first synchronizer. The NOR logic gate performs a NOR logical operation of the sleep signal and the output of the first synchronizer, and the resulting output is provided as an input to the second synchronizer.
The first synchronizer may generate the first select signal by synchronizing the input signal to a negative edge of the faster signal. The second synchronizer is designed to generate the second select signal by synchronizing the input to the negative edge of the slower clock signal. Due to the synchronization, glitches are avoided at the output of the AND gates. Due to the feedback loop (resulting from the above connections), the 0 to 1 transition on one select line always follows the 1 to 0 transition on the other select line. A short dead period (i.e., no clock signal generated) may be present on the output of the AND gate between the two transitions, but such a situation may be acceptable when glitches are avoided.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.